FIG. 1 shows a transcoder board of a Motorola GSM cellular radio base station system. The board supports 30 traffic channels and provides interfaces between a time division multiplex highway on the cellular radio side and a 2.048 Mbit/s serial CEPT link on the telephone switch side. TDM interface 10 and CEPT interface 11 respectively provide the inputs and outputs for coded and decoded voice respectively on the cellular radio side and the switch side respectively. Each traffic channel is realised using a 40 MIP/80 MHz digital signal processor labelled XCDR1-XCDR30. A TDM highway 12 on the left of the figure carries GSM compressed speech information (or for a data call, rate adapted data) and a CEPT link 13 on the right carries uncompressed speech information (or, for a data call, rate adapted data). The direction TDM to CEPT is called the uplink and the direction CEPT to TDM is called the downlink.
FIG. 2 shows a simplified first level decomposition of the architecture of one of the transcoders (e.g. XCDR1) of FIG. 1. The four functions represented by bubbles 20, 21, 22, and 23 are necessary to support the transcoding required by one single traffic channel. An SIO interrupt 20 performs the functions specified in GSM 08.60 and is activated every 125 microseconds interrupt. The uplink bubble 22 represents all the processing required to perform the GSM speech decoding specified in GSM 06.10 and the uplink GSM discontinuous transmission functions specified by GSM 06.31. It also performs, for a data call, rate adaption functions as per GSM 08.20. The downlink bubble 21 represents all the processing required to perform the GSM speech encoding specified in GSM 06.10 and the downlink GSM discontinuous transmission functions specified by GSM 06.31. It also represents, for a data call, rate adaptation functions as per GSM 08.20. The kernel bubble 23 comprises routines to schedule the uplink and downlink tasks in the order specified in GSM 06.10, GSM 08.60 GSM 03.05 and GSM 06.31, and for a data call, GSM 08.20, GSM 08.60 and GSM 03.05. The kernel times itself from the interrupts that the SIO 20 receives every 125 microseconds and allocates a downlink to uplink time slicing mechanism of 2-1. This provides two consecutive 125 microsecond timeslots for downlink processing followed by one timeslot for uplink processing.
It is a draw back that the SIO 20 reduces the amount of time left for the other three bubbles to such an extent that one DSP is required per traffic channel. Thus, the requirement for 30 DSPs on a single transcoder board to support 30 channels makes the equipment very expensive.
The 2-1 time slicing mechanism has two main flaws. First, a subchannel may be given an opportunity to execute even if there are no tasks available for that subchannel to perform. Second, if a subchannel's task completes before the end of the timeslot allocated to it, no other task may be performed in the remaining time, which therefore becomes idle or wasted. The fixed time slicer prohibits one subchannel's task from being executed during the other subchannel's time slice period.
There is a need for an improved transcoder.